Team engineering · 2026
A complete LDO competition record: design, hardware, and test preparation
This page restores the full project chain behind the Zengyi Huichuang Cup (曾益慧创杯) of the 10th National College Student IC Innovation and Entrepreneurship Competition. The team received First Prize in the Central China Regional Final and Second Prize in the National Final. This page separates that team result, my bounded contribution, and preparation-only material at every stage.
Project map
Four connected stages, with different evidence levels
- 01
Team design & simulation
1.8 V CMOS LDO
A transistor-level LDO in SMIC 180 nm CMOS with a PMOS pass device, bandgap reference, OTA, feedback network, bias generation, and compensation. - 02
Physical workflow
Layout-level evaluation
Top-level layout integration, Calibre DRC/LVS/PEX workflow, and post-layout analysis without a clean-signoff, tapeout, or fabricated-silicon claim. - 03
Team hardware task
Regional-final semi-discrete LDO
BJT characterization and component selection, followed by a 25 V-to-12 V semi-discrete feedback LDO and regulation, stability, transient, and thermal evaluation. - 04
Preparation record
National-stage automated testing
IECUBE and LabVIEW preparation for instrument control, test sequencing, voltage-accuracy, line/load-regulation and dropout scans, data logging, and result logic.
Team CMOS design flow
From circuit architecture to documented simulation evidence
The preliminary-stage team project targeted a 1.8 V LDO in SMIC 180 nm CMOS for a documented 3-5 V input range and a 1 µF external output capacitor. The design integrated a PMOS pass device, bandgap reference, OTA error amplifier, feedback divider, bias network, and loop compensation.
The team report records output, load and line regulation, quiescent current, PSRR, dropout, and STB analyses across selected temperatures and process conditions. The values below are report-level simulation evidence, not independently owned results or fabricated-device measurements.
Target output
Team CMOS design with a documented 3-5 V input range and 1 µF external output capacitor.
Quiescent current
Range documented in the team technical report; simulation only.
PSRR at 1 kHz
Reported team simulation range across the evaluated conditions.
Phase margin
Reported post-layout stability range; not a silicon measurement.
Physical workflow
Layout integration, LVS evidence, and post-layout stability
The archived team record includes a top-level layout, a Calibre LVS comparison marked CORRECT, PEX workflow, and post-layout simulation. The evidence supports exposure to the physical-design and extraction flow; it does not support a clean DRC sign-off, manufacturability, or tapeout claim.
Regional-final hardware
A separate semi-discrete LDO task, not a fabricated-chip test
The regional-final stage moved from CMOS design documentation to hands-on component work. Within the team activity, candidate BJTs were characterized and selected, and a 25 V-to-12 V semi-discrete feedback LDO was assembled, debugged, and evaluated. This hardware was separate from the 1.8 V CMOS design.
The public record preserves the engineering sequence while withholding restricted task images and unarchived measurement numbers.
- 01
Characterize TIP42C/TIP32C and BD139/BD135 candidates
- 02
Select and match devices; calculate the feedback and compensation network
- 03
Assemble and debug a 25 V-to-12 V semi-discrete feedback LDO
- 04
Evaluate regulation, dropout, stability, load transient, and thermal behavior
National-stage test workflow
IECUBE and LabVIEW preparation, stated at its actual maturity
The national-stage material shifted the emphasis to automated IC test: PWS/DIO/DMM instrument control, load switching, voltage-accuracy and line/load-regulation scans, dropout detection, data capture, and result logic on an IECUBE platform with LabVIEW.
The current project archive contains official-stage notes, training material, and a historical op-amp exercise used for structural learning. It does not contain a completed LDO VI, exported device measurements, or verified PASS/FAIL evidence. I therefore present this stage as preparation, not as a completed software or silicon-test deliverable.
Interpretation boundary
What this project demonstrates—and what it does not
Supported
- Selected contributions within a team analog-IC workflow.
- Exposure to circuit, layout, extraction, and post-layout analysis.
- Team-based semi-discrete hardware characterization and debugging.
- Preparation for structured automated-test sequencing and data handling.
- First Prize in the Central China Regional Final and Second Prize in the National Final as a team competition result.
Not claimed
- Independent ownership of the LDO or a complete circuit block.
- Clean DRC sign-off, tapeout, fabrication, or post-silicon validation.
- A completed LDO LabVIEW platform or archived national-stage measurements.
- A completed end-to-end IC design-to-test platform.